Servers which act as information processing devices with a cache memory have been known. The cache memory is incorporated into a CPU (Central Processing Unit) or an arithmetic processing unit and disposed between a core section, functioning as an arithmetic section included in the CPU, and a main memory. The cache memory, which can be accessed more quickly than the main memory, stores data or instructions that are accessed at high frequency. The arithmetic processing unit loads data or instructions from the cache memory that can be accessed faster than the main memory, thereby shortening memory access time and improving the performance of the information processing device.
As one type of such cache memory, a sector cache is known which has cache memory divided into a plurality of zones referred to as sectors. In such a sector cache, the cache memory is divided into two types of sectors, so that one sector stores data that is used repeatedly, whereas the other stores data that is used less frequently.
Furthermore, to debug such a sector cache, a cache hit check function is used to determine whether data at a given memory address is stored in the cache memory. For example, the cache hit check function can be used for debugging compilers or hardware.
To read such a cache hit check result, a cache memory read bus or a dedicated transfer bus can be used.
Now, referring to an example of FIG. 10, the configuration of a cache unit which performs a pipeline operation for reading a cache hit check result will be described below. As illustrated in FIG. 10, the cache unit includes a cache memory, an instruction set storage unit, an instruction control unit, a priority logic circuit, a cache access circuit, a tag matching circuit, an LRU (Least-Recently-Used) circuit, a sector information decision circuit, a buffer, and an external interface.
The instruction set storage unit stores a set of instructions such as prefetch instruction codes or cache hit check instruction codes. The instruction control unit reads the cache hit check instruction code from the instruction set storage unit, and issues the resulting instruction to the priority logic circuit. The priority logic circuit determines the priority of processing an entered instruction. The cache access circuit accesses a cache memory by using the target access address to read a tag and LRU information.
The tag matching circuit compares the tag having been read by the cache access circuit with the tag at the target access address. Upon determining that there was a cache hit, the sector information decision circuit determines whether the sector may be set to 0 or 1. The LRU circuit stores the use sectors and the use frequency of each cache way. The buffer stores the cache hit check result. The cache hit check result stored in the buffer is transferred to the external interface.
Now, referring to FIG. 11, a method for reading cache hit check results via the cache memory read bus will be described below. As illustrated in FIG. 11, a pipeline operation reads a Hit bit, a hit_way bit, a sector 0/1_num bit, and a sector bit via the bus. Here, the pipeline operation refers to the sequential steps of determining the priority of commands to be executed by the priority logic circuit “P,” accessing the cache memory to read a tag “T,” matching tags “M,” selecting data and storing it in the buffer “B,” and redirecting data “R.”
As illustrated in FIG. 11, in the case of a cache hit as a result of matching tags in tag matching “M,” the Hit bit is determined to be “1” and a cache hit way number, i.e., a hit_way bit is determined. Then, in “B” for selecting data and storing it in the buffer, the Hit bit and the hit_way bit are available for data selection. However, the cache hit sector information (the sector 0/1_num bit and the sector bit in the example of FIG. 11) becomes accessible after a one-cycle delay relative to the data selection cycle, resulting in the pipeline operation being performed twice.
Now, referring to FIG. 12, a method for reading cache hit check results via the dedicated transfer bus will be described below. As illustrated in FIG. 12, the dedicated transfer bus is used to redirect cache hit check results. This allows the cache hit check result to be read in a single pipeline operation without taking into account the timing for data selection.
Patent Document 1: Japanese Laid-open Patent Publication No. 08-335177
As can be seen in the foregoing, the aforementioned method for using the cache memory read bus to read a cache hit check result requires performing two successive pipeline operations, thereby causing the cache hit check result to be read in a complicated manner. On the other hand, the aforementioned technique for using the dedicated transfer bus to read a cache hit check result requires an additional dedicated transfer bus, thereby causing an increase in manufacturing costs.